module RF(
        input [4:0] R_Reg1, // Read register number 1
        input [4:0] R_Reg2, // Read register number 2
        input [4:0] W_Reg, // Write register number
        input [31:0] W_data,  // Write data
        input clk,
        input rst,
        input RegWr, // GRF write enable
        output [31:0] R_data1,  // Read data 1
        output [31:0] R_data2   // Read data 2
    );

    reg [31:0] registersFile[0:31];
    integer i=0;

    // reset registers
    always @(posedge clk) begin
        if(rst) begin
            for(i=12;i<32;i=i+1) begin
                registersFile[0]<=32'd0;
                registersFile[1]<=32'd1;
                registersFile[2]<=32'd2;
                registersFile[3]<=32'd3;
                registersFile[4]<=32'd4;
                registersFile[5]<=32'd5;
                registersFile[6]<=32'd6;
                registersFile[7]<=32'd7;
                registersFile[8]<=32'd8;
                registersFile[9]<=32'd9;
                registersFile[10]<=32'h00005000;
                registersFile[11]<=32'h00006000;
                registersFile[i]<=32'd1;
            end
        end

      // write registers or flash registers
        else begin
            if(RegWr) begin
                if(W_Reg!=5'd0) begin
                    registersFile[W_Reg]<=W_data;
                end
                else
                    registersFile[W_Reg]<=registersFile[W_Reg];
            end
        end
    end

    // read registers
    assign R_data1=registersFile[R_Reg1];
    assign R_data2=registersFile[R_Reg2];
endmodule
